Method of making flip chip

ABSTRACT

Disclosed is a method for manufacturing a flip chip, in which a gold typically used in a flip chip manufacturing is adhered by conductive adhesives, wherein the method comprises steps of depositing a metal seed layer on a substrate; applying and patterning a photoresist or a dry film; forming a gold bump by electroplating; patterning the seed layer; forming an insulating layer on the seed layer and upper end of the gold bump; and patterning an insulating layer. Accordingly, it is possible to manufacture a flip chip, in which electrical function between bumps can be evaluated, with less cost.

CROSS-REFERENCE TO RELATED REISSUE APPLICATION

This application is a continuation reissue application of applicationSer. No. 16/274,191 filed Feb. 12, 2019, which is an application forreissue of U.S. Pat. No. 8,048,793.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims under 35 U.S.C. §119(a) the benefit of KoreanPatent Application No. 10-2007-0089905 filed Sep. 5, 2007, the entirecontents of which are incorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a flip chip packaging technique, inwhich a chip and a substrate are electrically and mechanically connectedwith each other after the chip is flipped so as to allow a pad of thechip and the substrate to face each other.

BACKGROUND ART

A flip chip package has a small size and has superior electriccharacteristic and reliability in comparison with a package formed by awire bonding technique. The flip chip package is obtained by directlybonding a semiconductor chip and a printed circuit board (PCB) substrateby using a metallic bump. Gold, copper and solder, etc. are applied asthe metal bump. Among these, a flip-chip using a gold bump is typicallybonded to a substrate by using conductive adhesives. Different from achip using solder bumps, such a flip chip using the gold bump hasrecently been popular in a display field because it doesn't includeharmful element such as lead to environment and human health and hassuperior bonding reliability.

A method for forming a gold bump includes an electroplating method, avacuum depositing method, and a method forming a stud bump by wirebonding. Among these, the electroplating is most advantageous due to asimple manner and the low manufacturing costs.

A research for manufacturing a gold bump of a flip chip by using thiselectroplating method has been actively proceeded. For example, Koreanpatent publication NO. 10-2006-0044929 discloses a method for improvingnon-uniformity of a thickness of the gold bump in such a manner thatmetal with a low melting point is plated on a bump formed by plating oran alloy having a dome shape is formed thereon. However, after aformation of a gold bump by electroplating, the entire metallic seedlayer, except for the gold bump, is etched so that only the gold bumpremains on a wafer. Therefore, there is a disadvantage in that it isimpossible to evaluate the electrical characteristics of the gold bumpand a flip chip package bonded through electrical connection with thegold bump.

Korean patent registration NO. 10-0574986 discloses a method for forminga bump through an electroplating for a flip chip connection. A seedlayer is formed for electroplating, and a shielding layer and aphotosensitive mask are formed on the seed layer. Then, the exposedshielding layer, which has undergone a photolithography process and adeveloping process, is removed through dry etching, and a bump is formedon the exposed seed layer according to a plating method.

However, in the method according to the invention, the gold bump isformed by electroplating after the metal patterning and the shieldinglayer are formed. Therefore, it is necessary that an electrode wiringfor forming the gold bump is formed when the metal pattern is formed, ora metallic seed layer for plating is formed and moved on a top of aninsulating layer. Typically, the electrode wire is an unnecessary metalwire in an actual chip so that it has to be removed again after the goldbump is formed. Therefore, an additional process is necessary before andafter the gold bump is formed thereby causing inconvenience.

As a similar example, a method for manufacturing a gold bump on analuminum substrate by an electroplating method is announced [reference:John H. Lau, C. P. Wong, Ning-Cheng Lee, 0. W. Ricky Lee, ElectronicsManufacturing with Lead-free, Halogen-free, and Conductive-adhesivematerials, 4.1-4.9 (2003)]. The process as shown in FIG. 1 is performedin the announced reference. That is, according to the method, aninsulating layer is formed on an aluminum pad and the top of the pad,and a metal seed layer for electroplating of a gold bump is formed againon the upper part of the insulating layer. Then, after a formation ofthe gold bump, the metal seed layer applied for plating is finallyremoved. Similar to the disclosed invention, this method requiresforming and removing process of a metal seed layer to performelectroplating, and, thus, a manufacturing procedure becomes toocomplicated. Also, conventionally, a mask for photolithography, which isused for plating the gold bump, and a mask for photolithography, whichis used in patterning an insulating layer formed on the top of aconductive film, are separately manufactured.

The above information disclosed in this Background Art section is onlyfor enhancement of understanding of the background of the invention andtherefore it may contain information that does not form the prior artthat is already known in this country to a person of ordinary skill inthe art.

SUMMARY

Therefore, the present invention has been made in view of theabove-mentioned problems, and it is an object of the present inventionto provide a method for evaluating the electrical connection betweengold bumps and a method for improving a flip chip manufacturing processin forming a flip chip.

According to the present invention, a metal seed layer used inelectroplating for forming a bump is directly used as metal pattern forforming electrical connection between bumps, so that an electricalfunction between bumps can be evaluated, and it is possible to omit theprocesses of forming and removing an electrode wire only forelectroplating, which have been essential in the prior art.

According to an aspect of the present invention, there is provided aflip chip comprising: an insulating layer arranged on a substrate; ametal patterned seed layer arranged on the insulating layer; and a platebump layer formed on the metal seed layer, wherein the metal pattern isformed at a side of the plate bump, and is formed by patterning themetal seed layer.

It is preferable that the substrate is one selected from the groupconsisting of a silicon wafer, a compound semiconductor, quartz, glass,and ceramic material.

The insulating layer preferably comprises SiO₂ and Si₃N₄.

The seed layer preferably comprises an adhesive layer and an electrodelayer.

The adhesive layer preferably comprises titanium, and the electrodelayer comprises copper or gold.

According to another aspect of the present invention, there is provideda flip chip manufacturing method comprising: (a) forming a seed layer ona substrate by using a conductive thin layer; (b) applying andpatterning a photoresist or a dry film; (c) forming a gold bump byelectroplating; (d) patterning the seed layer; (e) forming an insulatinglayer on the seed layer and the upper end of the gold bump; and (f)applying and patterning a photoresist or a dry film so as to pattern theinsulating layer.

It is preferable that the patterning of steps (b) and (f) are performedby photolithography. Suitably, a photolithography mask used in thepatterning processes of step (b) is the same as that of step (f).

It is preferable that the polarity of the photoresist or the dry film ofstep (b) and that of step (f) are opposite.

Also, it is preferable that the patterning process of step (d) comprisesapplying and patterning a photoresist or a dry film and etching aportion of the conductive thin film on which portion the photoresist orthe dry film is not, so as to form a metal pattern for electricalconnection between gold bumps.

In the present invention, it is possible to omit the process of formingand removing an electrode wire by directly utilizing a metal seed layer,which is used for plating, as a metal pattern for electrical connectingbetween bumps. Therefore, the cost of material and a process cost can belowered. Also, it is possible to evaluate an electrical function betweenthe bumps by using such a metal pattern so that a flip chip having highreliability can be manufactured.

Also, it is possible to unify a mask for photolithography, which is usedfor plating a gold bump in such a manner that the polarity of aphotoresist or a dry film is opposite, and a mask for photolithography,which is used for pattering an insulating layer formed at an upper partof a conductive film, so that an additional unit manufacturing cost canbe reduced. Also, a daisy chain, etc. can be formed by patterning a seedlayer for electroplating so that electrical function of a flip chippackage can be evaluated.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will become more apparent from the following detaileddescription when taken in conjunction with the drawings in which:

FIG. 1 is a schematic view illustrating a conventional procedure ofmanufacturing a gold bump;

FIG. 2 is a schematic view illustrating a structure where an insulatinglayer is formed on the upper part of a substrate;

FIG. 3 is a view illustrating a structure where a conductive thin filmfor plating is formed on the upper part of an insulating layer;

FIG. 4 is a view illustrating a structure where a plating wall is formedat an upper part of a conductive thin film so as to plate a gold bump,in which the plating wall is made from photoresist or a dry film;

FIG. 5 is a view illustrating a structure where gold is formed byelectroplating so as to form a gold bump;

FIG. 6 is a view illustrating a structure where a photoresist or a dryfilm has been removed;

FIG. 7 is a view illustrating a structure where photolithography isperformed after a photoresist or a dry film is applied so as to etch aconductive thin film;

FIG. 8 is a view illustrating a structure where a metal etching processis performed so as to pattern a conductive thin film;

FIG. 9 is a view illustrating a structure where a photoresist or a dryfilm is removed;

FIG. 10 is a view illustrating a structure where an insulating layer isformed;

FIG. 11 is a view illustrating a structure where photolithography isperformed after a photoresist or a dry film is applied so as to etch aninsulating layer;

FIG. 12 is a view illustrating a structure where an insulating layer isetched;

FIG. 13 is a view illustrating a structure where a photoresist or a dryfilm is removed; and

FIG. 14 is a view illustrating a flip chip manufactured through theprocesses of FIGS. 2 to 13.

DETAILED DESCRIPTION

Hereinafter reference will now be made in detail to various embodimentsof the present invention, examples of which are illustrated in theaccompanying drawings and described below. While the invention will bedescribed in conjunction with exemplary embodiments, it will beunderstood that present description is not intended to limit theinvention to those exemplary embodiments. On the contrary, the inventionis intended to cover not only the exemplary embodiments, but alsovarious alternatives, modifications, equivalents and other embodiments,which may be included within the spirit and scope of the invention asdefined by the appended claims.

As shown in FIG. 2, an insulating layer 12 is formed so as to preventelectrical connection between a substrate 10 and an upper bump. Examplesof the insulating layer 12 include SiO₂, Si₃N₄, and the like.

As shown in FIG. 3, a conductive thin film 14 is formed so as to be usedas a metal seed layer in electroplating. At this time, the conductivethin film 14 is divided into an adhesion layer and an electric wirelayer (an electrode layer). Preferably, as the adhesive layer forimproving bonding force of the conductive thin film 14, titanium (Ti)may preferably be formed with a height of about 10 nm to 100 nm. As theelectrode layer functioning as an electrical passage, copper (Cu) orgold (Au), etc. may suitably be formed with a height of about 100 nm to1,000 nm.

FIG. 4 is a structure where a photoresist or a dry film 16 is applied soas to form the shape of a gold bump 18 before electroplating of the goldbump 18. Photolithography may be performed by using a mask coated withchrome for patterning. It is preferable that the thickness of thephotoresist or the dry film is about 20 μm. Moreover, the size of thegold bump can be made bigger or smaller than the size of the chip pad,when necessary.

As shown in FIG. 5, gold is electroplated so as not to exceed the heightof the patterned photoresist or the dry film 16. It is preferable thatthe height of the gold bump is about 10 nm to 19 μm.

As shown in FIG. 6, the photoresist or dry film 16 is removed when thegold bump bumps 18 is are completely formed by electroplating. The goldbumps 18 constitute a plate bump layer 19.

In order to achieve an electrical connection between bumps, a process ofpatterning the conductive thin film 14 used as a seed layer in platingis performed. As shown in FIG. 7, for example, a photoresist or dry film22 is disposed on the conductive thin film 14 and patterned byphotolithography using a new mask to provide a first portion 14A coveredby the patterned photoresist 22 and a second portion 14B not covered bythe patterned photoresist 22.

A metal etching process is then performed so as to remove the secondportion 14B of the conductive thin film 14, to which the photoresist orthe dry film 22 is not disposed. Titanium (Ti) can be etched byhydrofluoric acid (HF) diluted solution, Au can be etched by iodinationpotassium (KI) solution, and Cu can be etched by ferric chloride (FeCl₃)aqueous solution. Through this etching process, the shape in which theconductive thin film 14 is patterned can be obtained, as shown in FIG.8.

FIG. 9 shows a structure where the photoresist or dry film 22 used foretching of the conductive thin film 14 has been removed.

As shown in FIG. 10, an insulating layer 26 is formed so as to protectthe thin conductive film 14 and achieve insulation from externalenvironment. The insulating layer 26 includes insulating layers 26A, 26Band 26C that are formed on different surfaces. SiO₂, Si₃N₄, etc. maysuitably be used as the insulating layer 26.

As shown in FIG. 11, a photoresist and dry film 24 is disposed on theinsulating layer 26, and patterning is performed through thephotolithography process, which provides the patterned photoresist film24 on the insulating layers 26A and 26B but not on the insulating layer26C, so as to achieve patterning of the insulating layer 26. Suitably,the mask used in this photolithography may be the same as the mask usedin the process of FIG. 4, except that the polarity of the photoresist ordry film 24 is changed. For example, in a case where the photoresist ordry film 16 used in FIG. 4 is positive, the photoresist or dry film 24used in FIG. 11 is negative so as to achieve a patterning having anopposite shape. Through such a process, two processes can be performedby using one mask.

As shown in FIG. 12, the insulating layer 26 26C is etched so as toexpose the surface of the gold bump 18 while the insulating layers 26Aand 26B are maintained under the patterned photoresist film 24.

As shown in FIG. 13, the photoresist or dry film 24 is removed, whichwas applied to etch the insulating layer 26 26C.

FIG. 14 is a top view of a flip-chip manufactured through the processesof FIGS. 2 to 13, which includes thereon the insulating layer 12 formedbetween the substrate 10 and the conductive film 14, the gold bump 18formed by electroplating, and the electrically connecting layer (metalpatterned seed layer) 20 formed by patterning the conductive thin filmused as the seed layer in electroplating.

The present flip chips and manufacturing methods thereof can be appliedto various areas. For example, it is possible to bond a core memory chipand a non-memory chip and stack a horizontal multi chip and a verticalmulti chip, in the fields of high-end electronic machines, including,but not limited to, portable multimedia machines, such as cellularphones, and flat panel machines.

The invention has been described in detail with reference to preferredembodiments thereof. However, it will be appreciated by those skilled inthe art that changes may be made in these embodiments without departingfrom the principles and spirit of the invention, the scope of which isdefined in the appended claims and their equivalents.

The invention claimed is:
 1. A flip chip comprising: an insulating layerarranged on and directly contacted with a substrate, wherein theinsulating layer covers the substrate; a metal patterned seed layerarranged on the insulating layer and directly contacted with theinsulating layer; and a plate bump layer formed on the metal patternedseed layer, wherein one or more plate bumps are formed; wherein a metalpattern is formed at a side of the plate bump, and is formed bypatterning the metal patterned seed layer; wherein the metal pattern isat least a part of the metal patterned seed layer, and forms electricalconnection between the plate bumps.
 2. The flip chip as claimed in claim1, wherein the substrate is one selected from the group consisting of asilicon wafer, a compound semiconductor, quartz, glass, and ceramicmaterial.
 3. The flip chip as claimed in claim 1, wherein the insulatinglayer comprises SiO₂ or Si₃N₄.
 4. The flip chip as claimed in claim 1,wherein the seed layer comprises an adhesive layer and an electrodelayer.
 5. The flip chip as claimed in claim 4, wherein the adhesivelayer comprises titanium, and the electrode layer comprises copper orgold.
 6. A flip chip manufacturing method comprising: (a) forming a seedlayer on a substrate by using a conductive thin layer; (b) applying andpatterning a photoresist or a dry film; (c) forming gold bumps byelectroplating; (d) patterning the seed layer to form a metal pattern;(e) forming an insulating layer on the seed layer and the upper end ofthe gold bumps; and (f) applying and patterning a photoresist or a dryfilm so as to pattern the insulating layer; wherein the metal patternforms electrical connection between the gold bumps, and the polarity ofthe photoresist or a dry film in step b) is opposite to the polarity ofphotoresist or a dry film in step f).
 7. The flip chip manufacturingmethod as claimed in claim 6, wherein the patterning of steps (b) and(f) are performed by photolithography.
 8. The flip chip manufacturingmethod as claimed in claim 7, wherein a photolithography mask used inthe patterning processes of step (b) is the same as that of step (f). 9.The flip chip manufacturing method as claimed in claim 6, wherein thepatterning process of step (d) comprises applying and patterning aphotoresist or a dry film and etching a portion of the conductive thinfilm layer on which portion the photoresist or the dry film is not, soas to form a metal pattern for electrical connection between gold bumps.10. The method of claim 6, wherein the step (b) of applying andpatterning a photoresist or a dry film comprises: forming a firstphotoresist layer over the seed layer; and patterning the firstphotoresist layer with a first mask to form a plurality of openingsthrough the first photoresist layer to expose the seed layer in each ofthe plurality of openings; wherein the step (c) of forming gold bumpscomprises electroplating gold on the exposed seed layer in the pluralityof openings, in which the seed layer works as an electrode forelectroplating so that an electrode wire does not have to be formed foreach of the gold bumps; wherein subsequent to electroplating, the firstphotoresist layer covering the seed layer is removed to provide anintermediate structure comprising the substrate, the seed layer on thesubstrate, and the gold bumps on the seed layer; wherein the step (d) ofpatterning the seed layer to form a metal pattern comprises: forming asecond photoresist layer over the intermediate structure such that thesecond photoresist layer covers two of the gold bumps, covers a firstportion of the seed layer that interconnects the two gold bumps, anddoes not cover a second portion of the seed layer, subsequently etchingthe second portion of the seed layer that is not covered by the secondphotoresist layer while maintaining the two gold bumps and the firstportion of the seed layer that are covered by the second photoresistlayer, and subsequently removing the second photoresist layer to providethe metal pattern comprising the first portion of the seed layer thatinterconnects the two gold bumps; wherein the step of (e) forming aninsulating layer provides the insulating layer on the upper end of thegold bumps and also on the first portion of the seed layer thatinterconnects the two gold bumps; wherein the step of (f) applying andpatterning a photoresist or a dry film comprises: forming a thirdphotoresist layer over the insulating layer, patterning the thirdphotoresist layer using a second mask such that the third photoresistlayer stays over the insulating layer formed on the first portion of theseed layer that interconnect the two gold bumps while the insulatinglayer on the upper end of the gold bumps is exposed, subsequentlyetching the exposed insulating layer on the upper end of the gold bumpsto expose the upper end of the gold bump while maintaining the thirdphotoresist layer over the insulating layer formed on the first portionof the seed layer that interconnect the two gold bumps, andsubsequently, removing the third photoresist layer to provide a flipchip device comprising the substrate and the gold bumps formed over thesubstrate, wherein the two gold bumps are interconnected by the firstportion of the seed layer, wherein the insulating layer remains over thefirst portion of the seed layer that interconnects the two gold bumps;wherein the photoresist of the first photoresist layer in step (b) andthe photoresist of the third photoresist layer have opposite polarities.11. The method of claim 10, wherein etching the second portion of theseed layer exposes a portion of the substrate, wherein subsequent toremoving the second photoresist layer the portion of the substrate isstill exposed, wherein the insulating layer is formed on the portion ofthe substrate in addition to on the upper end of the gold bumps and onthe first portion of the seed layer that interconnects the two goldbumps, wherein the third photoresist layer formed over the insulatinglayer is also over the portion of the substrate, wherein the thirdphotoresist layer formed over the portion of the substrate remains afterpatterning the third photoresist layer, wherein the third photoresistlayer formed over the portion of the substrates remains after etchingthe exposed insulating layer, wherein after removing the thirdphotoresist layer, the insulating layer over the portion of thesubstrate is exposed in the flip chip device.
 12. The method of claim10, wherein the first and second masks are the same.
 13. The method ofclaim 10, wherein a single mask is used as the first mask in the step(b) and the second mask in the step (f).
 14. The method of claim 10,wherein the substrate comprises an insulation layer on top such that theseed layer is formed on the insulation layer of the substrate.
 15. Themethod of claim 10, wherein the photoresist of the first photoresistlayer has a positive polarity, and the photoresist of the thirdphotoresist layer has a negative polarity.
 16. The method of claim 10,wherein in the step (c) gold is electroplated to a level that does notexceed a height of the first photoresist layer.
 17. The method of claim10, wherein the gold bumps formed in the step (c) have a height in arange of about 10 nm to 19 μm.
 18. The method of claim 10, wherein theseed layer comprises an adhesion layer and an electrode layer.
 19. Themethod of claim 18, wherein the adhesion layer comprises titanium. 20.The method of claim 18, wherein the adhesion layer has a thickness ofabout 10 nm to 100 nm.
 21. The method of claim 18, wherein the electrodelayer comprises copper.
 22. The method of claim 18, wherein theelectrode layer comprises gold.
 23. The method of claim 18, wherein theelectrode layer has a thickness of about 100 nm to 1000 nm.
 24. Themethod of claim 6, wherein the step (b) of applying and patterning aphotoresist or a dry film comprises: forming a first photoresist layerover the seed layer, and patterning the first photoresist layer with afirst mask to form a plurality of openings through the first photoresistlayer to expose the seed layer in each of the plurality of openings;wherein the step (c) of forming gold bumps comprises electroplating goldon the exposed seed layer in the plurality of openings, in which theseed layer works as an electrode for electroplating so that an electrodewire does not have to be formed for each of the gold bumps; whereinsubsequent to electroplating, the first photoresist layer covering theseed layer is removed to provide an intermediate structure comprisingthe substrate, the seed layer on the substrate, and the gold bumps onthe seed layer; wherein the step (d) of patterning the seed layer toform a metal pattern comprises: forming a second photoresist layer overthe intermediate structure such that the second photoresist layer coverstwo of the gold bumps, covers a first portion of the seed layer thatinterconnects the two gold bumps, and does not cover a second portion ofthe seed layer, subsequently etching the second portion of the seedlayer that is not covered by the second photoresist layer whilemaintaining the two gold bumps and the first portion of the seed layerthat are covered by the second photoresist layer, and subsequentlyremoving the second photoresist layer to provide the metal patterncomprising the first portion of the seed layer that interconnects thetwo gold bumps; wherein the step of (e) forming an insulating layerprovides the insulating layer on the upper end of the gold bumps andalso on the first portion of the seed layer that interconnects the twogold bumps; wherein the step of (f) applying and patterning aphotoresist or a dry film comprises: forming a third photoresist layerover the insulating layer, patterning the third photoresist layer usinga second mask such that the third photoresist layer stays over theinsulating layer formed on the first portion of the seed layer thatinterconnect the two gold bumps while the insulating layer on the upperend of the gold bumps is exposed, subsequently etching the exposedinsulating layer on the upper end of the gold bumps to expose the upperend of the gold bump while maintaining the third photoresist layer overthe insulating layer formed on the first portion of the seed layer thatinterconnect the two gold bumps, and subsequently, removing the thirdphotoresist layer to provide a flip chip device comprising the substrateand the gold bumps formed over the substrate, wherein the two gold bumpsare interconnected by the first portion of the seed layer, wherein theinsulating layer remains over the first portion of the seed layer thatinterconnects the two gold bumps; wherein the photoresist of the firstphotoresist layer in step (b) and the photoresist of the thirdphotoresist layer have opposite polarities.
 25. The method of claim 24,wherein etching the second portion of the seed layer exposes a portionof the substrate, wherein subsequent to removing the second photoresistlayer the portion of the substrate is still exposed, wherein theinsulating layer is formed on the portion of the substrate in additionto on the upper end of the gold bumps and on the first portion of theseed layer that interconnects the two gold bumps, wherein the thirdphotoresist layer formed over the insulating layer is also over theportion of the substrate, wherein the third photoresist layer formedover the portion of the substrate remains after patterning the thirdphotoresist layer, wherein the third photoresist layer formed over theportion of the substrates remains after etching the exposed insulatinglayer, wherein after removing the third photoresist layer, theinsulating layer over the portion of the substrate is exposed in theflip chip device.
 26. The method of claim 24, wherein the substratecomprises an insulation layer on top such that the seed layer is formedon the insulation layer of the substrate.
 27. The method of claim 24,wherein the photoresist of the first photoresist layer has a positivepolarity, and the photoresist of the third photoresist layer has anegative polarity.
 28. The method of claim 24, wherein the seed layercomprises an adhesion layer and an electrode layer.